Static, random access memories (SRAMs) employ a number of cells, each for storing a single binary bit of information. Typical SRAM cell structures include what is commonly referred to as a four transistor, two resistor (4T-2R) SRAM cell and what is commonly referred to as a six transistor (6T) SRAM cell. A (4T-2R) SRAM cell is illustrated in (prior art) FIG. 1 of the drawing generally designated by the number 100. SRAM cell 100 is shown to include four, N-channel, transistors, which are designated 110, 112, 114, and 116, and two (load) resistors, which are designated 120 and 122. Transistor 110 is configured as a transfer transistor with the transistor source (or drain) connected to a bit (input) line, which is designated 130. The gate of transistor 110 is connected to a word (control) line, which is designated 132. The drain (or source) of transistor 110 is coupled by resistor 120 to the power supply potential, which is represented by a line 134. Transistor 112 is configured as a pull-down transistor with the transistor source connected to circuit ground, with the transistor gate coupled by resistor 122 to power supply line 134, and with the transistor drain connected to the drain of transistor 110. Transistor 114 is also configured as a pull-down transistor with the transistor source connected to circuit ground, with the transistor gate connected to the drain of transistor 110, and with the transistor drain connected to the gate of transistor 112. Finally, transistor 116 is also configured as a transfer transistor with the transistor source connected to the gate of transistor 112, with the transistor gate connected to word line 132, and with the transistor drain connected to a bit (output) line, which is designated 140. The lines connecting the cross-coupling gates and drains of the pull-down transistors are designated 150 and 152.
A six transistor (6T) SRAM cell is illustrated in (prior art) FIG. 2 generally designated by the number 200. SRAM cell 200 is shown to include four, N-channel, transistors, which are designated 210, 212, 214, and 216, and two, P-channel, (load) transistors, which are designated 220 and 222. The transistors are configured with the source of transistor 210 connected to a bit (input) line, which is designated 230, with the transistor gate connected to a word (control) line, which is designated 232, and with the transistor drain connected to a node which is connected to the source of transistor 220, to the drain of transistor 212, and to the gate of both transistors 214 and 222. Connected to another node is the gate of both transistors 220 and 212, the source of transistor 222, the drain of transistor 214, and the source of transistor 216. The drain of both transistors 220 and 222 are connected to the power supply potential, which is represented by a line 234; and, the source of both transistors 212 and 214 are connected to circuit ground. The gate of transistor 216 is connected to word line 232; and, the drain of the transistor is connected to a bit (output) line, which is designated 240.
In the implementation of high density SRAMs, the cell size is one of the more critical parameters, as it determines the total area of the memory array and, therefore, the chip size. For poly-silicon-resistor load (4T-2R) SRAM cells, the first poly-silicon layer and the active island layer, which define the pull-down transistor that is designated 114 in FIG. 1 and the transfer transistor that is designated 116 in FIG. 1, ultimately become the limiting layers in determining the cell size for array sizes larger than one million bits. In the conventional planar layout, the size of the pull-down transistor (114) accounts for a significant portion of the cell area. This is because the pull-down transistor (114) size must be around three times that of the transfer transistor (116) to prevent the state of the cell from being upset when transfer transistor (116) is turned on when the state of the cell is being read. The drawn gate width of the pull-down transistor also needs to include the portion that extends over the field region to account for misalignment and critical dimension variation. The need to connect the cross-coupled gates and drains of the pull-down transistors (112 and 114) further aggravates the layout density problem. In addition, the need to pick up the sources of the pull-down transistors (112 and 114) requires additional active island area and metal interconnect.
In dynamic RAMs (DRAMs) the trench has been used to implement the storage capacitor. (See, for example, M. Wada et al, "A Folded Capacitor Cell (F.C.C) For Future Megabit DRAMs," IEDM Tech. Dig., p.244-247 (1984); Shigeru Nakajima et al, "An Isolation-Merged Vertical Capacitor Cell For Large Capacity DRAM," IEDM Tech. Dig., p.240-243 (1984); and Kunio Nakamura et al, "Buried Isolation Capacitor (BIC) Cell For Megabit MOS Dynamic RAM," IEDM Tech. Dig., p.236-239 (1984).) More recently, the trench has been used to implement both the storage capacitor and the transfer transistor in high density DRAMs. (See, for example, W. F. Richardson et al, "A Trench Transistor Cross-Point DRAM Cell," IEDM Tech. Dig., p.714- 717.) In the latter case, the substrate is used as a ground plate for the capacitor. A very deep trench as well as a very complicated refill/etch/refill process is required to achieve the desired structure. Both the capacitor capacity and the transistor channel length vary in proportion to the trench depth and the variations in the refill/etch/refill processes. Also, the basic DRAM cell concepts do not apply directly to SRAM cells.
For static RAMs, a cell with poly-silicon load resistor implemented in the trench has been proposed to solve the layout density problem of the second poly-silicon (resistor) layer. (See, for example, Yoshio Sakai et al, "A Buried Giga-Ohm Resistor (BGR) Load Static RAM Cell, Tech. Dig., Symposium On VLSI Tech., p.6-7 (1984).) This approach, however, does not solve the first poly-silicon layer and the active island layer layout density problems which are more critical in SRAM's with one million bits or more. In fact, this buried-gigaohm load resistor occupies additional island area compared to that of conventional planar layouts.
The reader may also find of interest Daisuke Ueda et al, "Deep-Trench Power MOSFET With An Ron Area Product Of 160 mohms-square mm," IEDM Tech. Dig., p. 638-641 (1986); H-R Chang et al, "Ultra Low Specific On-Resistance UMOS FET,"IEDM Tech. Dig., p. 642-645 (1986); Antoine Tamer et al, "Numerical Comparison Of DMOS Power Transistors," IEEE T-ED vol. ED-30 no. 1, p. 76 (January 1983); and Satwinder Malhi et al, "Characteristics And Three-Dimensional Integration Of MOSFET's In Small-Grain LPCVD Polycrystalline Silicon," "IEEE T-ED vol. ED-32 no., section IX, p. 273-281 (2 Feb. 1985).